Why does Skylake (SKL) exhibit L2 writebacks during a read-only workload that exceeds L3 cache size?

Why does the Intel Skylake (SKL) architecture exhibit L2 writebacks during a read-only workload that exceeds the L3 cache size, and what are the underlying factors contributing to this behavior?

The Intel Skylake (SKL) architecture exhibits L2 writebacks during a read-only workload that exceeds the L3 cache size due to its non-inclusive L3 cache design. Here are the underlying factors contributing to this behavior:

Non-Inclusive L3 Cache: Unlike previous architectures, Skylake's L3 cache is non-inclusive. This means that data evicted from the L2 cache does not necessarily get stored in the L3 cache1. Instead, it can be written back directly to memory.

Cache Eviction Policies: When the L2 cache needs to evict data, it checks the state of the cache lines. If the data is marked as modified (dirty), it may be written back to memory instead of being moved to the L3 cache1. This can happen even during read-only workloads if the cache lines were previously modified.

Cache Prefetching: Skylake's prefetching mechanisms can bring data into the L2 cache that is not currently needed. If this data exceeds the L3 cache size, it may result in L2 writebacks to memory1.

Dynamic Cache Management: The cache management policies in Skylake are dynamic and based on heuristics such as reuse probability and sharing between cores. These policies determine whether a cache line should be dropped, evicted to the L3 cache, or written back to memory1.

These factors contribute to the observed L2 writebacks during read-only workloads that exceed the L3 cache size in the Skylake architecture.